The present invention relates generally to memory arrays and memory cells thereof. The present invention also relates to Random Access Memory (RAM), DRAM, SRAM, and Flash memory devices. The present invention is additionally related to techniques and devices for reading information from a memory. The present invention is also related to cell current address-sensitivity and techniques for stabilizing sense amplifiers utilized in association with memory arrays and memory cells thereof.
Several types of memory devices can be provided as internal storage areas in data processing system or computer. As utilized herein, the term xe2x80x9cmemoryxe2x80x9d generally refers to data storage configured in the form of integrated circuit chips. Several different types of memory are currently utilized in commercial applications. One type is known as Random Access Memory (RAM). RAM is generally utilized as a main memory in a computer. The acronym RAM generally refers to read and write memory in which data is written into RAM and read from RAM. Such a memory arrangement stands in contrast to ROM, which permits data to be read only. Most RAM is volatile, which means that RAM requires a steady flow of electricity to maintain its contents.
Basic operations of semiconductor memory devices such as dynamic random access memories (DRAMs), static random access memories (SRAMs), and flash memories thus involve reading and writing of data. DRAM (Dynamic Random Access Memory) is a form of semiconductor memory that store information in integrated circuits containing capacitors. Because capacitors lose their charge over time, DRAM boards generally include logic circuits to refresh (i.e., recharge) the DRAM chips continuously. While a DRAM is being refreshed, it cannot be read by the associated processor. If the process must read the RAM while it is being refreshed, one or more wait states may occur. SRAM (Static Random Access Memory) is a form of semiconductor memory based on the logic circuit known as a flip-flop, which retains information as long as there is enough power to run the device.
Dynamic random access memories (DRAMs) are thus data storage devices that store data as a charge on a storage capacitor. A DRAM typically includes an array of memory cells that each include a storage capacitor and an access transistor for transferring charge to and from the storage capacitor. Each memory cell is addressed by a word line and accessed by a bit line. The word line controls the access transistor such that the access transistor controllably couples and decouples the storage capacitor to and from the bit line for writing and reading data to and from the memory cell. The data is read using a differential sensing circuit. Differential sensing is used in different types of DRAM""s, including synchronous dynamic random access memory (SDRAM). An SDRAM is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory.
In a typical DRAM complementary bit lines are coupled to a differential sense amplifier During operation, the bit lines are precharged and equilibrated to a common intermediate voltage. It is common to precharge the bit lines to xc2xd VCC prior to accessing a memory cell. The memory cell is then coupled to one of the bit lines and changes the voltage of the bit line. That is, the charge or lack of charge stored on the memory cell is shared with the charged bit line. The resultant charge will either be increased by a memory cell having a charge, or decreased by an unprogrammed memory cell. The differential voltage level between the complementary bit lines can then be detected and the respective bit lines amplified to either Vcc or Vss.
The operations that write data vary according to the type of memory, however, the operations that read data are generally similar because of similarities in memory architectures. In a conventional two-dimensional memory architecture, a word line connects to the gates of memory cell transistors in a row of memory cells, and a bit line connects to the sources or drains of the memory cell transistors in a column of memory cells. The operation of reading data in a typical semiconductor memory device is controlled by a signal, referred to as a read enable signal. A memory cell is selected by enabling a word line and a bit line connected to the memory cell. Therefore, reading data from the memory cell is possible only after the word line and the bit line are enabled.
Flash memory is a type of nonvolatile memory utilized widely in the semiconductor arts. In a flash memory, data can be read by sensing the amount of current on a bit line. Therefore, a flash memory utilizes a current sense amplifier, which can sense and amplify the amount of current, to read data in the flash memory. The time taken for sensing the data stored in the memory cell depends on the time required for the sensed current to reach a stable state. For example, in the case where the word line voltage turns on the cell transistor (i.e., the memory cell transistor is erased and has a low threshold voltage), sensing a stable current greater than a predetermined reference current indicates a first data value.
Sensing a stable current less than the reference current (e.g., when the memory cell transistor is programmed to a high threshold voltage) can indicate a second data value. A cell in which the memory cell transistor turns on when the corresponding word line is enabled can be referred to as a turned-on cell. A cell in which the memory cell transistor remains off when the corresponding word line is enabled can be referred to as a turned-off cell. When the word line is enabled late, the speed at which data is sensed is reduced because a longer wait is required before the sensed current stabilizes.
A problem associated with modern memory array configurations, particularly those involving memory devices such as Flash memory, SRAM and DRAM, involves the address-sensitivity of cell currents generated during read operations. During the read operation, the cell current is xe2x80x9caddress sensitivexe2x80x9d because of the existence of a source line resistance between the selected cell and an associated source line strap. Simply put, address sensitivity is due to differences in resistance. The present inventors have thus concluded, based on the foregoing, that a need exists to eliminate the address-sensitivity of the cell current. If this can be accomplished in a cost effective and efficient manner, the stability of the sense amplifier can be guaranteed. Additionally, such a solution would greatly reduce the effort of circuit designers to meet the quick evaluation of flash memory cell performance. The present inventors believe that the invention disclosed herein solves this important need.
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
It is therefore one aspect of the present invention to provide an improved memory array apparatus and method.
It is another aspect of the present invention to provide an improved RAM method and apparatus.
It is yet another aspect of the present invention to provide and improved DRAM method and apparatus.
It is still another aspect of the present invention to provide an improved SRAM method and apparatus.
It is also an aspect of the present invention to provide an improved flash memory method and apparatus.
It is an additional aspect of the present invention to provide an improved method and apparatus for stabilizing sense amplifiers utilized in association with memory arrays and memory cells.
The above and other aspects of the present invention can thus be achieved as is now described. A method and apparatus for stabilizing a sense amplifier utilized in a memory array of a semiconductor integrated circuit is described herein. A memory cell of the memory array may be selected, wherein the selected memory cell is associated with a sense amplifier. A cell current associated with the selected memory cell and a reference current associated with a reference memory cell can be generated. Thereafter, the reference current may be synchronized with a plurality of address inputs to eliminate a source line resistance associated with the selected memory cell, thereby resulting in a stabilization the sense amplifier by the elimination of associated address sensitivity.
The reference current can be synchronized with address inputs utilizing a synchronous selector. A plurality of Y-address inputs are generally connected to the synchronous selector, such that the source line resistance is Y-address sensitive. A read operation to read information from the selected memory cell may be performed, wherein the source line resistance impacts the cell current. Generally a source line is associated with a plurality of memory cells of the memory array. The source line can be configured to include at least one source line strap, such that the at least one source line strap that is based on a particular number of column multiplexers (MUX). The bit lines are generally connected to the source line. The memory array can comprise a Flash memory array, an SRAM array, and/or a DRAM array.
The present invention thus introduces an address-dependent reference current for a sense amplifier and additionally introduces a new algorithm for placing a source line strap according to number of column MUX. In this manner, the stability of the sense amplifier can be assured and the efforts of circuit designers to meeting the rapidly changing needs of flash cell quick performance evaluation can be achieved.